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LTC3544 Quad Synchronous Step-Down Regulator: 2.25MHz, 300mA, 200mA, 200mA, 100mA FEATURES

DESCRIPTION
The LTC (R)3544 is a quad, high efficiency, monolithic synchronous buck regulator using a constant-frequency, current mode architecture. The four regulators operate independently with separate run pins. The 2.25V to 5.5V input voltage range makes the LTC3544 well suited for single Li-Ion/polymer battery-powered applications. 100% duty cycle provides low dropout operation, extending battery runtime in portable systems. Low ripple Burst Mode(R) operation increases efficiency at light loads, further extending battery runtime with typically only 20mV of ripple. Switching frequency is internally set to 2.25MHz, allowing the use of small surface mount inductors and capacitors. The internal synchronous switches increase efficiency and eliminate the need for external Schottky diodes. Low output voltages are easily supported with the 0.8V feedback reference voltage. The LTC3544 is available in a low profile (0.75mm) (3mm x 3mm) QFN package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 5994885.

High Efficiency: Up to 95% Four Independent Regulators Provide Up to 300mA, 200mA, 200mA and 100mA Output Current 2.25V to 5.5V Input Voltage Range 2.25MHz Constant-Frequency Operation No Schottky Diodes Required Extremely Low Channel-to-Channel Transient Crosstalk Low Ripple (20mVP-P) Burst Mode Operation: IQ = 70A (All Channels On) 0.8V Reference Allows Low Output Voltages Shutdown Mode Draws <1A Supply Current Current Mode Operation for Excellent Line and Load Transient Response Overtemperature Protected Low Profile (3mm x 3mm) 16-Lead QFN Package
APPLICATIONS

Cellular Telephones Personal Information Appliances Wireless and DSL Modems Digital Still Cameras Media Players Portable Instruments
TYPICAL APPLICATION
High Efficiency Quad Step-Down Converter
VIN 2.25V TO 5.5V VOUT2 1.5V 200mA 4.7F CER 4.7F CER 4.7H 93.1k 107k LTC3544 3.3H 133k 107k RUN300 SW300 VFB300 GNDA PGND RUN100 SW100 VFB100 118k 10H 59k VOUT1 1.2V 100mA 4.7F CER VCC PVIN
Efficiency vs Load Current, 300mA Channel, All Other Channels Off
100 90 EFFICIENCY 0.1 POWER LOSS (W) LOSS VOUT = 2.5V TA = 25C 0.01 1
RUN200B SW200B VFB200B
RUN200A SW200A VFB200A
3.3H
EFFICIENCY (%)
VOUT3 0.8V 200mA 4.7F CER
80 70 60 50 40 30 20 10 0 0.0001
100k
VOUT4 1.8V 300mA 4.7F CER
0.001 VIN = 2.7V VIN = 3.6V VIN = 4.2V 0.001 0.01 0.1 LOAD CURRENT (A) 1
3544 TA01b
0.0001
3544B TA01a
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LTC3544 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW RUN200B SW100 12 RUN100 17 11 VFB100 10 VFB300 9 5 SW200A 6 PGND 7 PVIN 8 SW300 RUN300 GNDA VCC
Input Supply Voltage .....................................-0.3V to 6V RUNx ............................................. -0.3V to (VIN + 0.3V) VFBx ................................................ -0.3V to (VIN + 0.3V) SWx ............................................... -0.3V to (VIN + 0.3V) 300mA P-Channel Source Current (DC) (Note 8) ..450mA 300mA N-Channel Sink Current (DC) (Note 8) ......450mA 200mA P-Channel Source Current (DC) (Note 8) ..300mA 200mA N-Channel Sink Current (DC) (Note 8) ......300mA 100mA P-Channel Source Current (DC) (Note 8) ..200mA 100mA N-Channel Sink Current (DC) (Note 8) ......200mA Peak 300mA SW Sink and Source Current (Note 8) ................................................................600mA Peak 200mA SW Sink and Source Current (Note 8) ................................................................400mA Peak 100mA SW Sink and Source Current (Note 8) ................................................................200mA Operating Temperature Range ...................-40C to 85C Junction Temperature (Notes 3, 4) ........................ 125C Storage Temperature Range ....................-65C to 125C
16 15 14 13 VFB200B 1 VFB200A 2 RUN200A 3 SW200B 4
UD PACKAGE 16-LEAD (3mm x 3mm) PLASTIC QFN TJMAX = 125C, JA = 68C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3544EUD#PBF LEAD BASED FINISH LTC3544EUD TAPE AND REEL LTC3544EUD#TRPBF TAPE AND REEL LTC3544EUD#TR PART MARKING LCXM PART MARKING LCXM PACKAGE DESCRIPTION 16-Lead (3mm x 3mm) Plastic QFN PACKAGE DESCRIPTION 16-Lead (3mm x 3mm) Plastic QFN TEMPERATURE RANGE -40C to 85C TEMPERATURE RANGE -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL VIN VFBREGx VFBREGx VLOADREG PARAMETER Input Voltage Range Regulated Feedback Voltage (Note 5) General Characteristics
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V unless otherwise noted.
CONDITIONS

MIN 2.25 0.792 0.784
TYP
MAX 5.5
UNITS V V V %/V %
0.8 0.8 0.05 0.5
0.808 0.816 0.25
Reference Voltage Line Regulation (Note 5) Output Voltage Load Regulation (Note 6)
VIN = 2.25V to 5.5V
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LTC3544 ELECTRICAL CHARACTERISTICS
SYMBOL IS PARAMETER Input DC Bias Current Active Mode (Four Regulators Enabled) Sleep Mode (Four Regulators Enabled) Shutdown fOSC VRUN(HIGH) VRUN(LOW) ISWx IRUNx IVFBx tSS VUVLO Oscillator Frequency RUNx Input High Voltage RUNx Input Low Voltage SWx Leakage RUN Leakage Current VFBx Leakage Current Soft-Start Period Undervoltage Lockout VFB = 7.5% to 92.5% Full Scale
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V unless otherwise noted.
CONDITIONS VFB = 0.7V, ILOAD = 0A, 2.25MHz VFB = 0.9V, ILOAD = 0A, 2.25MHz MIN TYP 825 70 0.1 VIN = 3V VIN = 2.5V to 5.5V 2.25

MAX 1100 80 2 2.7 0.3
UNITS A A A MHz MHz V V A A nA s V
1.8 1.0 0.1
VRUN = 0V, VSW = 0V or 5.5V, VIN = 5.5V VIN = 5.5V
1 1 80 1200 2.25
0.1 650 875 1.9
Individual Regulator Characteristics Regulator SW300 - 300mA IPK IS300 RPFET RNFET IPK IS200 RPFET RNFET IPK IS200 RPFET RNFET IPK IS100 RPFET RNFET Peak Switch Current Limit Input DC Bias Current-Reg SW300 Only Burst Mode Operation (Sleep) RDS(ON) of P-Channel FET (Note 7) RDS(ON) of N-Channel FET (Note 7) Peak Switch Current Limit Input DC Bias Current-Reg SW200A Only Burst Mode Operation (Sleep) RDS(ON) of P-Channel FET (Note 7) RDS(ON) of N-Channel FET (Note 7) Peak Switch Current Limit Input DC Bias Current-Reg SW200B Only Burst Mode Operation (Sleep) RDS(ON) of P-Channel FET (Note 7) RDS(ON) of N-Channel FET (Note 7) Peak Switch Current Limit Input DC Bias Current-Reg SW100B Only Burst Mode Operation (Sleep) RDS(ON) of P-Channel FET (Note 7) RDS(ON) of N-Channel FET (Note 7) VFB < VFBREG, Duty Cycle < 35% VFB = 0.9V, ILOAD = 0A, 2.25MHz ISW = 100mA ISW = -100mA VFB < VFBREG, Duty Cycle < 35% VFB = 0.9V, ILOAD = 0A, 2.25MHz ISW = 100mA ISW = -100mA VFB < VFBREG, Duty Cycle < 35% VFB = 0.9V, ILOAD = 0A, 2.25MHz ISW = 100mA ISW = -100mA VFB < VFBREG, Duty Cycle < 35% VFB = 0.9V, ILOAD = 0A, 2.25MHz ISW = 100mA ISW = -100mA 200 300 300 400 600 32 0.55 0.50 400 32 0.65 0.60 400 32 0.65 0.60 300 32 0.80 0.75 400 500 500 800 mA A mA A mA A mA A
Regulator SW200A - 200mA
Regulator SW200B - 200mA
Regulator SW100 - 100mA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The LTC3544E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls.
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LTC3544 ELECTRICAL CHARACTERISTICS
Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD)(68C/W). Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: The LTC3544 is tested in a proprietary test mode that connects VFB to the output of the error amplifier. Note 6: Load regulation is inferred by measuring the regulation loop gain. Note 7: The QFN switch on-resistance is guaranteed by correlation to wafer level measurements. Note 8: Guaranteed by long-term current density limitations.
TYPICAL PERFORMANCE CHARACTERISTICS
VREF vs Temperature at 2.25V, 3.6V, 5.5V
0.815 0.810 0805 VREF (V) 0.800 0.795 0.790 0.785 -50 VIN = 2.25V VIN = 3.6V VIN = 5.5V 0 50 TEMPERATURE (C) 100
3544 G01
Switching Frequency vs Supply Voltage and Temperature
3.0 ILOAD CHANNEL 100 = 50mA ALL CHANNELS OPERATING SWITCHING FREQUENCY (MHz) 100 90 80 EFFICIENCY (%) 2.5 70 60 50 40 30 fOSC -40C fOSC 0C fOSC 25C fOSC 80C 1.5 2 5 3 4 SUPPLY VOLTAGE (V) 6
3544 G02
Efficiency vs Load Current 300mA Channel. All Other Channels at 50% Peak Current
CHANNEL 200A ILOAD = 100mA ALL CHANNELS OPERATING
2.0
20 10
0 0.0001
VIN = 3.6V TA = 25C VOUT100 = 1.2V VOUT200A = 0.8V VOUT200B = 1.5V VOUT300 = 1.8V ALL OTHER CHANNELS LOADED 50% 0.001 0.01 0.1 LOAD CURRENT 300mA CHANNEL (A) 1
3544B G03
Burst Mode Operation 300mA Channel
VOUT300 50mV/DIV AC COUPLED SW300 5V/DIV VOUT200B 50mV/DIV AC COUPLED SW2B 5V/DIV
Burst Mode Operation 200mA, A-B Channels
VOUT100 50mV/DIV AC COUPLED SW100 5V/DIV
Burst Mode Operation 100mA Channel
IL 100mA/DIV 2s/DIV TA = 25C ILOAD = 20mA
3544 G04
IL 50mA/DIV
3544 G05
IL 50mA/DIV 2s/DIV TA = 25C ILOAD = 15mA 2s/DIV TA = 25C ILOAD = 12mA
3544 G06
VIN = 3.6V VOUT = 1.8V
VIN = 3.6V VOUT = 1.5V
VIN = 3.6V VOUT = 1.2V
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LTC3544 TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current 300mA Channel. All Other Channels Off
100 90 80 70 EFFICIENCY (%) EFFICIENCY (%) 60 50 40 30 20 10 0 0.0001 VIN = 2.25V VIN = 3.6V VIN = 4.2V VOUT = 1.8V TA = 25C ALL OTHER CHANNELS OFF 1
3544 G07
Efficiency vs Load Current 200mA Channel A. All Other Channels Off
100 90 80 70 60 50 40 30 20 10 0 0.0001 VOUT = 0.8V TA = 25C ALL OTHER CHANNELS OFF 0.01 0.1 0.001 LOAD CURRENT (A) 1
3544 G08
Efficiency vs Load Current 200mA Channel B. All Other Channels Off
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.0001 VIN = 2.25V VIN = 3.6V VIN = 4.2V VOUT = 1.5V TA = 25C ALL OTHER CHANNELS OFF 1
3544 G09
VIN = 2.25V VIN = 3.6V VIN = 4.2V
0.01 0.1 0.001 LOAD CURRENT (A)
0.001 0.01 0.1 LOAD CURRENT (A)
Efficiency vs Load Current 100mA Channel. All Other Channels Off
100 90 80 VOUT ERROR (%) 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.0001 VIN = 2.25V VIN = 3.6V VIN = 4.2V VOUT = 1.2V TA = 25C ALL OTHER CHANNELS OFF 1
3544 G10
Load Regulation All Channels
1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 0 100 200 LOAD (mA)
3544 G11
Start-Up Curves All Channels
VIN = 3.6V TA = 25C VOUT100 VOUT200A VOUT200B
100mA = 1.2V 200mA (A) = 0.8V 200mA (B) = 1.5V 300mA = 1.8V
Burst Mode OPERATION RIPPLE
VOUT300 RUNx
VIN = 3.6V 200s/DIV TA = 25C ALL CHANNELS UNLOADED 300 400
3544 G12
0.001 0.01 0.1 LOAD CURRENT (A)
Load Step Response 300mA Channel
VOUT300 100mV/DIV AC COUPLED IL 250mA/DIV ILOAD 250mA/DIV VIN = 3.6V 20s/DIV VOUT = 1.8V TA = 25C ILOAD = 600A TO 300mA
3544 G13
Load Step Response 200mA Channel A
VOUT200A 50mV/DIV AC COUPLED IL 250mA/DIV ILOAD 250mA/DIV VIN = 3.6V 20s/DIV VOUT = 0.8V TA = 25C ILOAD = 600A TO 200mA
3544 G14
Load Step Response 200mA Channel B
VOUT200B 50mV/DIV AC COUPLED
IL 250mA/DIV ILOAD 250mA/DIV VIN = 3.6V 20s/DIV VOUT = 1.5V TA = 25C ILOAD = 600A TO 200mA
3544 G15
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LTC3544 TYPICAL PERFORMANCE CHARACTERISTICS
Load Step Response 100mA Channel
VOUT100 50mV/DIV AC COUPLED VOUT100 1mV/DIV VOUT200A 1mV/DIV VOUT200B 1mV/DIV VOUT300 50mV/DIV VIN = 3.6V 20s/DIV VOUT = 1.2V TA = 25C ILOAD = 400A TO 100mA
3544 G16 3544 G17 VIN = 3.6V 40s/DIV TA = 25C 300mA LOAD STEP ON VOUT300 OTHER CHANNELS LOADED 50% OF MAXIMUM
Load Step Crosstalk
IL 100mA/DIV ILOAD 100mA/DIV
PFET RDS(ON) vs Supply Voltage
1.2 1.0 0.8 RDS(ON) () RDS(ON) () 0.6 0.4 0.2 0 2 2.5 3 3.5 300 200B 200A 100 4.5 4 VIN (V) 5 5.5 6 TA = 25C 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
NFET RDS(ON) vs Supply Voltage
TA = 25C
300 200B 200A 100 2 3 4 VIN (V) 5 6
3544 G17
3544 G16
PFET RDS(ON) vs Temperature
1.0 0.9 0.8 0.7 RDS(ON) () 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 300 200B 200A 100 90
3544 G18
NFET RDS(ON) vs Temperature
1.0 0.9 0.8 0.7 RDS(ON) () 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 50 0 TEMPERATURE (C) 300 200B 200A 100 100
3544 G19
VIN = 3.6V
VIN = 3.6V
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LTC3544 PIN FUNCTIONS
VFB200B (Pin 1): 200mA Regulator B Feedback Pin. This pin receives the feedback voltage from an external resistive divider across the output. VFB200A (Pin 2): 200mA Regulator A Feedback Pin. This pin receives the feedback voltage from an external resistive divider across the output. RUN200A (Pin 3): 200mA Regulator A Enable Pin. Forcing this pin to VIN enables the 200mA regulator (channel A), while forcing it to GND causes the regulator to shut off. SW200B (Pin 4): Switch Node Connection to Inductor for 200mA Regulator B. This pin connects to the drains of the internal power MOSFET switches. SW200A (Pin 5): Switch Node Connection to Inductor for 200mA Regulator A. This pin connects to the drains of the internal power MOSFET switches. PGND (Pin 6): Power Path Return Pin for Both 200mA Regulators and the 300mA Regulator. PVIN (Pin 7): Power Path Supply Pin for Both 200mA Regulators and the 300mA Regulator. This pin must be closely decoupled to PGND, with a 4.7F or greater ceramic capacitor. SW300 (Pin 8): Switch Node Connection to Inductor for 300mA Regulator. This pin connects to the drains of the internal power MOSFET switches. RUN300 (Pin 9): 300mA Regulator Enable Pin. Forcing this pin to VIN enables the 300mA regulator, while forcing it to GND causes the regulator to shut off. VFB300 (Pin 10): 300mA Regulator Feedback Pin. This pin receives the feedback voltage from an external resistive divider across the output. VFB100 (Pin 11): 100mA Regulator Feedback Pin. This pin receives the feedback voltage from an external resistive divider across the output. RUN100 (Pin 12): 100mA Regulator Enable Pin. Forcing this pin to VIN enables the 100mA regulator, while forcing it to GND causes the 100mA regulator to shut off. SW100 (Pin 13): Switch Node Connection to Inductor for 100mA Regulator. This pin connects to the drains of the internal power MOSFET switches. GNDA (Pin 14): Ground Pin for Internal Reference and Control Circuitry. Power path return for the 100mA regulator. VCC (Pin 15): Supply Pin for Internal Reference and Control Circuitry. Power path supply pin for the 100mA regulator. RUN200B (Pin 16): 200mA Regulator B Enable Pin. Forcing this pin to VIN enables the 200mA regulator (channel B), while forcing it to GND causes the regulator to shut off. Exposed Pad (Pin 17): Ground. Must be soldered to PCB.
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LTC3544 FUNCTIONAL DIAGRAMS
3 RUN200A 9 RUN300 15 VCC 14 GNDA 16 RUN200B 12 RUN100
SHDN 0.8V REF RUN LOGIC 5 SW200A IBIAS200A POWER FETs 2 VFB200A REG200A SW300 IBIAS300 POWER FETs 10 VFB300 REG300 7 PVIN 6 PGND REG200B IBIAS200B POWER FETs VFB200B 1 REG100 SW200B IBIAS100 POWER FETs VFB100 11 SW100 13 OSC
8
4
3544 FD01
REGULATOR BURST CLAMP SLOPE COMP 3 PVIN
VFBx
1
-
EA 0.8V
-
ITH VSLEEP SLEEP
-
ICOMP
+
10
+
+
BURST S Q RS LATCH R Q SWITCHING LOGIC AND BLANKING CIRCUIT
SOFT-START
ANTI SHOOTTHRU 4 SWx
IRCMP SHUTDOWN
0.8V VREF
OSC OSC
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-
3544 FD02
+
5 PGND
LTC3544 OPERATION
(Refer to Functional Diagrams)
The LTC3544 uses a constant-frequency current mode architecture. The operating frequency is set at 2.25MHz. All channels share the same clock and run in-phase. The output voltage for each regulator is set by an external resistor divider returned to the VFB pin. An error amplifier compares the divided output voltage with a reference voltage of 0.8V and regulates the peak inductor current accordingly. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The current into the inductor and the load increases until the peak inductor current (controlled by ITH) is reached. The RS latch turns off the top switch, turns on the bottom switch, and energy stored in the inductor is discharged through the bottom switch (N-channel MOSFET) into the load until the next clock cycle begins, or until the inductor current begins to reverse (sensed by the IRCMP comparator). The peak inductor current is controlled by the internally compensated ITH voltage, which is the output of the error amplifier. This amplifier regulates the VFB pin to the internal 0.8V reference by adjusting the peak inductor current accordingly. Burst Mode Operation To optimize efficiency, the LTC3544 automatically switches from continuous operation to Burst Mode operation when the load current is relatively light. During Burst Mode operation, the peak inductor current (as set by ITH) remains fixed at a low level and the PMOS switch operates intermittently based on load demand. By running cycles periodically, the switching losses are minimized. The duration of each burst event can range from a few cycles at light load to almost continuous cycling with short sleep intervals at moderate loads. During the sleep intervals, the load current is being supplied solely from the output capacitor. As the output voltage droops, the error amplifier output rises above the sleep threshold, signaling the burst comparator to trip and turn the top MOSFET on. This cycle repeats at a rate that is dependent on load demand.
VOUT100 VOUT200A VOUT200B VOUT300 RUNx
VIN = 3.6V 200s/DIV TA = 25C ALL CHANNELS UNLOADED
3544 G12
Figure 1. Regulator Soft-Start
Soft-Start Soft-start reduces surge currents on VIN and output overshoot during start-up. Soft-start on the LTC3544 is implemented by internally ramping the reference signal fed to the error amplifier over approximately a 1ms period. Figure 1 shows the behavior of the four regulator channels during soft-start. Short-Circuit Protection Short-circuit protection is achieved by monitoring the inductor current. When the current exceeds a predetermined level, the main switch is turned off, and the synchronous switch is turned on long enough to allow the current in the inductor to decay below the fault threshold. This prevents a catastrophic inductor current, run-away condition, but will still provide current to the output. Output voltage regulation in this condition is not achieved. DROPOUT OPERATION As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3544 is used at 100% duty cycle with low input voltage (see Thermal Considerations in the Applications Information section).
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LTC3544 APPLICATIONS INFORMATION
The basic LTC3544 application circuit is shown on the first page of this data sheet. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 1H to 10H. Its value is chosen based on the desired ripple current. Large inductor values lower ripple current and small inductor values result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in Equation 1. A reasonable starting point for setting ripple current for the 300mA regulator is IL = 120mA (40% of 300mA). IL = V VOUT 1 - OUT VIN ( )(L ) 1 (1)
Wurth TPC744029
Table 1. Representative Surface Mount Inductors
Part Number Sumida CDH2D09B Value (H) 10 6.4 4.7 3.3 10 6.8 4.7 3.3 10 6.8 4.7 3.3 DCR ( MAX) 0.47 0.32 0.218 0.15 0.50 0.38 0.210 0.155 0.67 0.39 0.28 0.17 MAX DC CURRENT (A) 0.48 0.6 0.7 0.85 0.50 0.65 0.80 0.95 0.49 0.61 0.70 0.87 W x L x H (mm3) 3.0 x 2.8 x 1.0
2.8 x 2.8 x 1.35
TDK VLF3010AT
2.8 x 2.6 x 1.0
CIN and COUT Selection In continuous mode, a worst-case estimate for the input current ripple can be determined by assuming that the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN, and amplitude IOUT(MAX). To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS IOUT(MAX ) VOUT ( VIN - VOUT ) VIN
The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 360mA rated inductor should be enough for most applications (300mA + 60mA). For better efficiency, choose a low DCR inductor. Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs. size requirements and any radiated field/EMI requirements than on what the LTC3544 requires to operate. Table 1 shows typical surface mount inductors that work well in LTC3544 applications.
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design. Note that the capacitor manufacturer's ripple current ratings are often based on 2000 hours of life (non-ceramic capacitors). This makes it advisable to further de-rate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple VOUT is determined by: 1 VOUT IL ESR + 8 * * COUT where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. For a fixed output
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LTC3544 APPLICATIONS INFORMATION
voltage, the output ripple is highest at maximum input voltage since IL increases with input voltage. Using Ceramic Input and Output Capacitors Higher value, lower cost, ceramic capacitors are now widely available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3544's control loop does not depend on the output capacitor's ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage Programming The output voltage is set by tying VFB to a resistive divider according to the following formula: R2 VOUT = 0.8 V 1+ R1 The external resistive divider is connected to the output allowing remote voltage sensing as shown in Figure 2.
0.8V VOUT 5.5V
Keeping the current in the resistors small maximizes the efficiency, but making them too small may allow stray capacitance to cause noise problems or reduce the phase margin of the control loop. It is recommended that the total feedback resistor string be kept to under 100k. To improve the frequency response of the control loop, a feed forward capacitor, CF, may be used. Great care should be taken to route the feedback line away from noise sources such as the inductor of the SW line. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3544 circuits: VIN quiescent current and I2R losses. VIN quiescent current loss dominates the efficiency loss at low load currents, whereas the I2R loss dominates the efficiency loss at medium to high load currents. 1. The quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from PVIN to ground. The resulting dQ/dt is the current out of PVIN that is typically larger than the DC bias current and proportional to frequency. Both the DC bias and gate charge losses are proportional to PVIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both
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R2 VFB LTC3544 GND
3544 F02
CF
R1
Figure 2. Setting the LTC3544 Output Voltage
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LTC3544 APPLICATIONS INFORMATION
top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses when in switching operation, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. Thermal Considerations The LTC3544 requires the package backplane metal to be well soldered to the PC board. This gives the QFN package exceptional thermal properties, making it difficult in normal operation to exceed the maximum junction temperature of the part. In most applications the LTC3544 does not dissipate much heat due to its high efficiency. In applications where the LTC3544 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part if it is not well thermally grounded. If the junction temperature reaches approximately 150C, the power switches will be turned off and the SW nodes will become high impedance. To avoid the LTC3544 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = PD * JA where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3544 in dropout at an input voltage of 2.5V, a total load current (all four regulators) of 800mA and an ambient temperature of 85C. From the Typical Performance graphs of switch resistance, the RDS(ON) of the 300mA P-channel switch at 85C can be estimated as 0.67. Therefore, power dissipated by the 300mA channel is: PD = ILOAD2 * RDS(ON) = 60mW Similar analysis on the other channels gives a total power dissipation of 138mW. For the 3mm x 3mm QFN package, the JA is 68C/W. Thus, the junction temperature of the regulator is: TJ = 85C + (0.138)(68) = 94.4C which is well below the maximum junction temperature of 125C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance RDS(ON). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD * ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady-state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 * CLOAD). Thus, a 10F capacitor charging to 3.3V would require a 250s rise time, limiting the charging current to about 130mA.
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LTC3544 APPLICATIONS INFORMATION
PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3544. These items are also illustrated graphically in Figures 3 and 4. Check the following in your layout: 1. The power traces, consisting of the PGND trace, the GNDA trace, the SW traces, the PVIN trace and the VCC trace should be kept short, direct and wide. 2. Does each of the VFBx pins connect directly to the respective feedback resistors? The resistive dividers must be connected between the (+) plate of the corresponding output filter capacitor (e.g., C13) and GNDA. If the circuit being powered is at such a distance from the part where voltage drops along circuit traces are large, consider a Kelvin connection from the powered circuit back to the resistive dividers. 3. Keep C8 and C9 as close to the part as possible. 4. Keep the switching nodes (SWx) away from the sensitive VFBx nodes. 5. Keep the ground connected plates of the input and output capacitors as close as possible. 6. Care should be taken to provide enough space between unshielded inductors in order to minimize any transformer coupling. Design Example As a design example, consider using the LTC3544 as a portable application with a Li-Ion battery. The battery provides VIN ranging from 2.8V to 4.2V. The demand at 2.5V is 250mA necessitating the use of the 300mA output for this requirement.
L4 VOUT1 R15 C13 R16 RUN100 C15
VCC 2.25V TO 5.5V
C8
GNDA
SW1000 RUN100 VFB100
VCC
GNDA
VFB200A VFB200B VFB300 VFB300
C1 GND
C4
VFB100
L1
L4
LTC3544 RUN200A L2 VOUT3 R5 C4 R6 VFB200A L3 VOUT2 R8 C10 R11 C12 VFB200B
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RUN200A SW200A SW200B SW200B PGND C9
RUN300 RUN200B PVIN SW300 SW300
RUN300 RUN200B VCC C9 L1 VOUT4 R2 C3 C2 C3 R3 PGND L2 L3 C10
SW200A
C6
PGND PVIN 2.25V TO 5.5V
C1
Figure 3. LTC3544 Layout Diagram
Figure 4. LTC3544 Suggested Layout
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13
LTC3544 APPLICATIONS INFORMATION
Beginning with this channel, first calculate the inductor value for about 35% ripple current (100mA in this example) at maximum VIN. Using a form of Equation 1: L4 = 2.5V 2.5V 1- = 4.5H 2.25MHz * 100mA 4.2V 200k are a good compromise between efficiency and immunity to any adverse effects of PCB parasitic capacitance on the feedback pins. Choosing 10A with 0.8V feedback voltage makes R7 = 80k. A close standard 1% resistor is 76.8k. Using: V R8 = OUT - 1 * R7 = 163.2k 0.8 The closest standard 1% resistor is 162k. An optional 20pF feedback capacitor may be used to improve transient response. The component values for the other channels are chosen in a similar fashion. Figure 5 shows the complete schematic for this example, along with the efficiency curve and transient response for the 300mA channel.
C10 4.7F 15 L2 4.7H R3 93.1k R4 107k L3 4.7H C3 4.7F R6 100k 3 5 2 RUN200A SW200A C6 20pF 16 4 1 RUN200B SW200B VFB200B LTC3544 RUN300 SW300 9 8 10 L4 4.7H C8 20pF R7 162k R8 76.8k VCC 7 PVIN RUN100 SW100 VFB100 12 13 11 L1 10H C5 20pF R1 59k R2 118k
For the inductor, use the closest standard value of 4.7H. A 4.7F capacitor should be sufficient for the output capacitor. A larger output capacitor will attenuate the load transient response, but increase the settling time. A value for CIN = 4.7F should suffice as the source impedance of a Li-Ion battery is very low. The feedback resistors program the output voltage. Minimizing the current in these resistors will maximize efficiency at very light loads, but totals on the order of
VSUPPLY 3.6V C9 4.7F
VOUT2 1.5V C2 4.7F
VOUT1 1.2V C1 4.7F
VOUT3 0.8V
VOUT2 2.5V C4 10F
VFB200A GNDA 14 PGND 6
VFB300
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Figure 5. Design Example Efficiency vs Output Current--300mA Channel, All Other Channels Off
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 VOUT = 2.5V TA = 25C VIN = 2.7V VIN = 3.6V VIN = 4.2V 1
3544B F05b
Transient Response
VOUT300 50mV/DIV AC COUPLED IL 250mA/DIV ILOAD 250mA/DIV
3544B F05c
0 0.0001
0.001 0.01 0.1 LOAD CURRENT (A)
VIN = 3.6V 20s/DIV VOUT = 2.5V TA = 25C LOAD STEP = 300A TO 300mA
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LTC3544 PACKAGE DESCRIPTION
UD Package 16-Lead Plastic QFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 0.05
3.50 0.05 1.45 0.05 2.10 0.05 (4 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 15 16 0.40 0.10 1 1.45 0.10 (4-SIDES) 2 PIN 1 NOTCH R = 0.20 TYP OR 0.25 x 45 CHAMFER
3.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6)
(UD16) QFN 0904
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC3544 RELATED PARTS
PART NUMBER LTC3405/LTC3405A LTC3406/LTC3406B LTC3407/LTC3407-2 LTC3409 LTC3410/LTC3410B LTC3411 LTC3412 LTC3441/LTC3442 LTC3443 LTC3446 LTC3531/LTC3531-3 LTC3531-3.3 LTC3532 LTC3544B LTC3547/LTC3547B LTC3548/LTC3548-1 LTC3548-2 LTC3561 DESCRIPTION 300mA IOUT, 1.5MHz, Synchronous Step-Down DC/DC Converters 600mA IOUT, 1.5MHz, Synchronous Step-Down DC/DC Converters Dual 600mA/800mA IOUT, 1.5MHz/2.25MHz, Synchronous Step-Down DC/DC Converters 600mA IOUT, 1.7MHz/2.6MHz, Synchronous Step-Down DC/DC Converter 300mA IOUT, 2.25MHz, Synchronous Step-Down DC/DC Converters 1.25A IOUT, 4MHz, Synchronous Step-Down DC/DC Converter 2.5A IOUT, 4MHz, Synchronous Step-Down DC/DC Converter 1.2A IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converters Monolithic Synchronous Buck Regulator with Dual VLDOTM Requlators 200mA IOUT, 1.5MHz, Synchronous Buck-Boost DC/DC Converters 500mA IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter 300mA, 2 x 200mA, 100mA Quad 2.25MHz Synchronous Buck DC/DC Converter Dual 300mA IOUT, 2.25MHz, Synchronous Step-Down DC/DC Converter Dual 400mA/800mA IOUT, 2.25MHz, Synchronous Step-Down DC/DC Converters 1.25A IOUT, 4MHz, Synchronous Step-Down DC/DC Converter COMMENTS 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20A, ISD < 1A, ThinSOTTM Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20A, ISD < 1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 10-Lead MSE, DFN Packages 96% Efficiency, VIN: 1.6V to 5.5V, VOUT(MIN) = 0.6V, IQ = 65A, ISD < 1A, DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26A, ISD < 1A, SC70 Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, 10-Lead MSE, DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, 16-Lead TSSOPE Package 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 50A, ISD < 1A, DFN Package 92% Efficiency, VIN: 2.7V to 5.5V, VOUT(MIN) = 0.4V, IQ = 140A, ISD < 1A, 3mm x 4mm DFN Package 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN): 2V to 5V, IQ = 16A, ISD < 1A, ThinSOT, DFN Packages 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 35A, ISD < 1A, 10-Lead MSE, DFN Packages 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 825A, ISD < 1mA, 3mm x 3mm QFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 8-Lead DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 10-Lead MSE, DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 240A, ISD < 1A, DFN Package
ThinSOT and VLDO are trademarks of Linear Technology Corporation
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16 Linear Technology Corporation
(408) 432-1900
LT 0308 REV A * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

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